TSMC's $23B 3nm Bet on Japan: Kumamoto Fab Gets a Leash

By Daniel Rao | TechPulse USA | October 21, 2026

TSMC has officially committed to building 3-nanometre chips in Japan — a milestone that makes the country only the third place on Earth with a certified frontier-logic fab. But read the fine print on Monday's $23 billion announcement and the victory lap gets awkward: Tokyo approved the upgrade while trimming the subsidy, and a chronic shortage of EUV lithography machines caps the new fab at just 6,000 wafers a month — an 87.5% haircut from the original blueprint. Japan's most advanced chip factory will arrive on a leash.

Photo: JASM's Kumamoto campus (file photo — the existing first fab; the second fab is still being built). TSMC's Japan subsidiary has been cleared to make 3nm chips at its second factory on this campus. Wikimedia Commons (CC BY-SA 4.0).

What TSMC actually announced

The announcement came not as a press conference but as a post on X from TSMC's Japan account — a thank-you note to the Japanese government with terms attached. Production and investment plans, the company wrote, "will be implemented in phases in response to market demand," and everything proceeds "on the premise of government support."

"Specific production and investment plans will be implemented in phases in response to market demand," TSMC said in its statement. The fab, it added, would help meet growing demand for advanced chips driven by artificial intelligence while serving customers in Japan and other markets.

The full statement is worth quoting because of how carefully it is hedged: "Moving forward, JASM will continue to work alongside our partners to provide cutting-edge technology to customers in Japan and around the world, using innovative green manufacturing technologies that are environmentally considerate, in order to meet the strong demand in the AI era," the company said.

Read it again. Every clause after the comma is conditional: in phases, on market demand, on the premise of government support. TSMC is the richest chipmaker on the planet — it just posted a 68.7% jump in quarterly profit — and even it is not writing this cheque without Tokyo standing next to the register.

48,000 wafers became 6,000 — that is the real story

The headline number everyone is repeating is $23 billion. ANI's reporting on the announcement puts it plainly: "total equipment investment in the venture expected to exceed $23 billion." Separately, TSMC's own statement, as relayed alongside Japan's trade ministry documents, confirms total Kumamoto capital spending exceeds $23 billion — approximately ¥3.63 trillion — across both facilities. Two statements, same figure, slightly different scopes; the point stands either way. This is TSMC's biggest bet on Japan yet.

But the number that should grab you is 6,000. When TSMC laid out the second Kumamoto fab's blueprint in February 2024, it called for 6nm and 12nm chips at 48,000 wafers a month — a volume-first plan aimed squarely at Japan's carmakers and industrial giants. On October 16, Japan's Ministry of Economy, Trade and Industry certified a radically different plan: 3nm chips at just 6,000 wafers a month.

That is an 87.5% reduction in output. It is not, as some early commentary suggested, a retreat. It is what happens when a fab trades mature-node mass production for the frontier node: 3nm manufacturing is colossally capital-intensive per wafer, and the equipment that makes it possible barely exists in the quantities the industry needs.

Tokyo trimmed the subsidy, not the ambition

Kumamoto I's quiet downgrade: 12–16nm phases out, 22–28nm takes over

METI's October 16 package also revised the FIRST Kumamoto fab: all 12–16nm production phases out; the plant concentrates on 22–28nm nodes (plus 40nm processes reserved for Japanese domestic customers) at 45,000 wafers per month across the subsidized footprint — 50,000 across the full plant. JASM attributes the revision to how automotive and industrial customer demand has evolved. The fab has run since late 2024, and was tested on July 28, 2026, when a magnitude 7.1 earthquake halted JASM Fab 1 for equipment inspections (max seismic intensity 5 at the site); analysts estimated a one-week shutdown at roughly $14 million in potential lost revenue (Focus Taiwan via TrendForce). It returned to normal operations — a data point worth keeping when Tokyo bets its advanced-logic future on a seismic island.

Here is the twist the press releases bury. Under Japan's semiconductor reindustrialisation programme, METI originally planned ¥732 billion (about $4.6 billion) in subsidies for the second fab under the old 6nm/12nm plan. With the revised 3nm blueprint certified, that figure has been adjusted down to ¥645.15 billion (about $4.1 billion) — reflecting the smaller initial production volume.

The first fab's subsidy was trimmed too, from ¥476 billion to ¥409.5 billion (about $2.6 billion), as METI revised its plan to concentrate Kumamoto I on 22–28nm production for cars, image sensors and industrial electronics. Across both plants, committed public support falls from ¥1.208 trillion to ¥1.055 trillion — roughly $6.7 billion.

"TSMC will probably need to invest $20 billion into a facility with 20,000 wafers per month, and the key is how much funding the Japanese government will provide," International Business Strategies CEO Handel Jones told EE Times when analysts first read the upgrade decision. That was the bet then; the arithmetic has only sharpened since. TSMC itself has signalled that the 6,000-wafer figure is a first phase, with expansion contingent on — the word keeps coming back — additional government support. METI, for its part, included an increased-support request in its fiscal 2027 preliminary budget.

The subsidy also comes with strings: under METI's certification conditions, JASM commits to operating the fab for ten years and to increasing production in the event of a domestic chip shortage — standard conditions on Japanese semiconductor subsidies, but conditions all the same.

The bottleneck is a Dutch machine

Why only 6,000 wafers a month? Because 3nm cannot be built without extreme ultraviolet lithography, and EUV is the most concentrated bottleneck in the global chip industry. One company on Earth makes commercial-scale EUV systems — ASML in the Netherlands, which we've covered before during ASML's earnings week — and it builds only 50 to 60 machines a year. Each costs well over $150 million, each takes months to install and qualify, and a 3nm line needs multiple tools running in concert across more than 20 critical lithography layers.

We checked METI's revised figures against the certified plan as relayed in the Japanese financial press — the arithmetic holds, and the ministry's own explanation centres on exactly this constraint: 3nm demands EUV tooling and a far heavier investment per wafer than the mature nodes it replaces. The 6,000-wafer ceiling is what ASML's production line and TSMC's global equipment queue can realistically support at a Japanese site during the 2026–2028 installation window, while TSMC simultaneously feeds its Arizona and Taiwan expansions.

"Given the progress of AI transformation, 3nm cutting-edge logic semiconductors that power AI are indispensable," Tomonari Nanbu, Director of METI's Information Industry Division, told reporters after the certification. It is the rare bureaucratic quote that doubles as strategy: Japan is not buying this fab for volume. It is buying optionality — a domestic foothold in the one node the AI era cannot live without.

Photo: the fabrication building at JASM's Kumamoto campus (file photo — the existing first fab, photographed in 2024). The second fab, now approved for 3nm, will be far smaller in initial output than originally planned: 6,000 wafers a month. Wikimedia Commons (CC BY-SA 4.0).

Arizona goes first, Japan goes second

Kumamoto's 3nm line is targeted for December 2028 — roughly a year after TSMC's second Arizona fab begins 3nm production in the second half of 2027. The sequence is deliberate, and it tells you how TSMC thinks: Taiwan first, then Arizona under the weight of American CHIPS Act money and political gravity, then Japan.

SemiAnalysis analyst Jeff Koch put the geography bluntly when he spoke to EE Times about the upgrade: "TSMC doesn't see this as a Japanese fab to serve Japanese customers. This is just an additional way for them to expand global 3-nm capacity quickly since the fab was already under construction." His forecast: real volume shipments from the fab in 2028.

That global framing is the point investors should not miss. The fab exists to serve TSMC's AI customers — the Nvidia-class accelerators that have Japanese hyperscalers and defence-adjacent buyers queuing — with supply that does not all sit in Taiwan. Koch noted the yields from TSMC's first Kumamoto fab are competitive, and Jones added that Japan still holds a deep pool of process and manufacturing engineers from its 1980s heyday. The site is real; the strategy is global; the Japanese flag on it is one of three.

The numbers underneath: AI demand and a record quarter

The upgrade was announced against the strongest quarter TSMC has ever reported. ET Manufacturing, carrying ANI's wire, reported a 68.7% year-on-year increase in net profit to $23.86 billion for the July–September quarter, with revenue up 50.9% to $46.72 billion. (TechPulse covered TSMC's record quarter separately; this is the context behind the chequebook.)

The company is betting that AI demand stays white-hot for a decade, and its technology math backs the urgency: TSMC's N3 process delivers roughly 70% more logic density than 5nm, about 15% better performance at the same transistor count, and 30% lower power consumption — the combination that lets AI accelerators scale without melting. The memory side of the AI race is running just as hard — see CXMT's memory claims that rattled the market — but logic is where the margin lives, and TSMC knows it.

There is also a Sony-shaped footnote. In August, TSMC and Sony Semiconductor Solutions agreed a joint venture, Advanced Vision Semiconductor Manufacturing Corp., to develop next-generation image sensors in Kumamoto, with commercial production scheduled for 2029, according to Focus Taiwan. JASM itself remains TSMC's vehicle — 86.5% owned, with Sony, Denso and Toyota holding the rest — so the Kumamoto campus is quietly becoming the centre of Japan's chip revival, one JV at a time.

The questions everyone is asking

What is JASM?

Japan Advanced Semiconductor Manufacturing is TSMC's Japanese subsidiary, a joint venture in which TSMC holds 86.5%, with Sony Semiconductor Solutions, Denso and Toyota as minority partners. It operates the Kumamoto fab campus; the first fab began volume production in late 2024, and the second fab — now certified for 3nm — is under construction.

When will Kumamoto make 3nm chips?

Commercial production is targeted for December 2028, under METI's certified plan. That makes the second Kumamoto fab Japan's first certified 3nm-capable logic facility, arriving roughly a year after TSMC's second Arizona fab starts 3nm production in the second half of 2027.

How much is Japan paying TSMC?

Committed public support across both Kumamoto fabs was revised to ¥1.055 trillion (about $6.7 billion) from ¥1.208 trillion: ¥645.15 billion (about $4.1 billion) for the second fab and ¥409.5 billion (about $2.6 billion) for the first. METI is considering raising the second fab's support further, with a request included in its fiscal 2027 preliminary budget — in exchange for a ten-year operation commitment and a pledge to prioritise domestic supply in a shortage.

Our take

Strip away the $23 billion and this deal is colder-eyed than it looks. Tokyo got what it wanted: a certified 3nm fab, the first outside Taiwan and South Korea, and a ten-year operating lock with a domestic-supply priority clause. It paid less than it planned to, because it tied the subsidy to the smaller first-phase volume — honest pricing, frankly, for a 6,000-wafer start. And TSMC got what it wanted: a government co-signer, a globally fungible 3nm line, and the option to scale if the subsidies follow.

The judgement call is who needs whom more. Koch's read — that this is global capacity with a Japanese address, not a Japanese fab — is almost certainly right. Japan's domestic customers do not yet have large 3nm demand; the chips Kumamoto makes in 2028 will feed the same AI customers Arizona and Taiwan feed. Europe, meanwhile, is watching all of this with open alarm — as Nvidia's Huang warning Germany about missing the AI wave showed, the continent understands the stakes even if it lacks the fabs. Japan now has a fab. The question is whether 6,000 wafers a month — a rounding error against global AI demand — counts as participation or decoration. On that, the second phase, and the FY2027 budget, will be the verdict. Watch the subsidy line, not the headline number.

Update, Oct. 21: the subsidy arithmetic is now fully visible. The second fab's maximum subsidy is ¥645.15 billion (~$4.1B), down from the ¥732 billion (~$4.6B) tied to the 2024 6nm/12nm plan; the FIRST fab's subsidy was cut in parallel, from ¥476 billion to ¥409.5 billion (~$2.6B) — taking total committed public support for the two-fab campus from ¥1.208 trillion to ¥1.055 trillion (~$6.7B) (techtimes, Oct 19, citing METI documents). METI has put a request for additional subsidy funds into its fiscal 2027 preliminary budget process — the decision that determines whether TSMC can raise the 6,000-wafer ceiling before mass production begins in December 2028.

Sources: ANI wire via ET Manufacturing and The Tribune (October 20, 2026); TechTimes (October 19, 2026), citing METI's certified revised plan documents; EE Times (Alan Patterson), with analyst comment from International Business Strategies CEO Handel Jones and SemiAnalysis analyst Jeff Koch; Focus Taiwan (image-sensor JV); TrendForce (JASM ownership, Arizona timeline).

Daniel Rao covers AI infrastructure and US–China tech competition for TechPulse USA.